1. Technical Field
The present invention relates generally to a semiconductor memory apparatus, and more particularly to a phase change memory apparatus.
2. Related Art
As shown in FIG. 1, a phase change memory cell (hereinafter also referred to as a “memory cell”) used in a conventional phase change memory apparatus utilizes germanium-antimony-tellurium (Ge2Sb2Te5: GST) as a phase change substance such that a combination of a GST and a diode comprising a phase change memory cell is connected between a bit line BL and a word line WL. Although not shown in FIG. 1, the phase change memory cell may be configured as a GST and transistor combination.
The GST can undergo a phase change of an amorphous phase or a crystalline phase through heat applied by an electrical current.
Information then can be recorded in the phase memory cell using the variable resistant characteristic of the GST, that is, the resistance value of the amorphous phase is relatively higher than the resistance value of the crystalline phase.
FIG. 2 shows a conventional X8 type phase change memory apparatus, in which input/output paths (I/O) are designed such that 8-bit data can be inputted/outputted through one time activation of a word line.
Referring to FIG. 2, a conventional phase change memory apparatus 1 includes a plurality of unit cell arrays ‘Unit Cell Array’, a row decoder 10, a column decoder 20, a write driver/sense amplifier array block 30, a global column switch block 40, a plurality of local row switch blocks 50, and a plurality of local column switch blocks 60.
As a word line WL is activated by the row decoder 10, unit cell arrays ‘Unit Cell Array’ in the row direction are selected.
Unit cell arrays ‘Unit Cell Array’ in the column direction are activated by the column decoder 20 and the local column switch blocks 60.
The write driver/sense amplifier array block 30 includes a plurality of write driver/sense amplifier arrays 31.
As eight global bit lines GBL<0:7> are selected by the global column switch block 40, write/read paths between the write driver/sense amplifier array block 30 and activated unit cell arrays ‘Unit Cell Array’ are defined.
Accordingly, 8-bit data can be written into or read out from the eight selected memory cells of the activated unit cell arrays ‘Unit Cell Array’ through input/output paths I/O<0:7>.
As shown in FIG. 3, a plurality of global bit lines GBL and a plurality of bit lines BL are disposed in the unit cell arrays ‘Unit Cell Array’.
A number of bit lines BL corresponding to a preset coding rate is connected to the global bit line GBL.
The global column switch block 40 includes a plurality of pass gates, four of which are shown in FIG. 3, block 40. One end from each input/output terminal of the respective pass gates is respectively connected to the global bit lines GBL.
The other four ends from the input/output terminals of four pass gates, which define a unit, are commonly connected to the write driver W/D and the sense amplifier S/A of the write driver/sense is amplifier array 31 as shown in FIG. 3.
Data input/output can occur by activating one of the four pass gates in response to column control signals GYSW<0:3> and GYSWB<0:3> provided from the column decoder 20.
In this case, the global bit line GBL connected to the activated pass gate corresponds to the global bit line GBL0 shown in FIG. 2.
As a result, in the X8 type phase change memory apparatus 1, one data is outputted from each of the activated unit cell arrays ‘Unit Cell Array’.
Meanwhile, to increase the number of input/output data as in an X16 or X32 type device with same memory capacity as that shown in FIG. 3, the number of data inputted/outputted from the unit cell arrays ‘Unit Cell Array’ connected to the one activated word line WL should be increased, and the design of input/output paths (I/O) should be changed correspondingly.
For example, a conventional X16 type phase change memory apparatus 2 as shown in FIG. 4 inputs/outputs two sets of data in each of the activated unit cell arrays ‘Unit Cell Array’ such that a total of 16-bit data is inputted/outputted through the input/output paths I/O<0:15>.
In order to input/output two sets of data in each of activated unit cell arrays ‘Unit Cell Array’, the circuit configuration of the column decoder 21, the write driver/sense amplifier array block 50, the global column switch block 41, and the local column switch is blocks 61 shown in FIG. 4 would need to be changed to be different from those shown in FIG. 3.
However, as described above, increasing the number of the input/output paths (I/O) means increasing the number of data inputted/outputted through the unit cell arrays ‘Unit Cell Array’ connected to the one activated word line WL, and this also means that the number of memory cells which are selected by the activated word line WL also increases as shown in FIG. 5.
Consequently, an increase in the amount of current flowing through the activated word line WL means a rise in the voltage level in the word line WL. This will likely degrade the current discharge capability of the diode or transistor connected to the GST. As a result, data recording cannot be precisely implemented and the reliability of cell data is apt to deteriorate due to decreased amount of current flowing through the GST from a bit line BL to a word line WL.